From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> The QEMU virt and spike machines currently export a riscv,isa string of "rv64imafdcsuh", but this obviously has illegal extensions in it. The presense of "su" is a QEMU bug, so add an entry for the valid portion of the isa string. Reported-by: Rob Herring <robh@xxxxxxxxxx> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@xxxxxxxxxx/ Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- Although the commit message says "a" string, I have added more than one isa string. My patched version of QEMU emits the full string with the multi letter extensions and I am not sure what the policy is for including them in the binding. Obviously I am more than willing to change the patch text if needed. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..59b942c5b9aa 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -77,6 +77,8 @@ properties: enum: - rv64imac - rv64imafdc + - rv64imafdch + - rv64imafdch_zicsr_zifencei_zba_zbb_zbc_zbs # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.37.1
