Added information about the S4 SOC Peripheral Clock controller in DT.
Signed-off-by: Yu Tu <yu.tu@xxxxxxxxxxx>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index a816b1f7694b..71be1dda15a2 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,s4-clkc.h>
/ {
cpus {
@@ -100,6 +102,30 @@ clkc_pll: pll-clock-controller@8000 {
#clock-cells = <1>;
};
+ clkc_periphs: periphs-clock-controller {
+ compatible = "amlogic,s4-periphs-clkc";
+ reg = <0x0 0x0 0x0 0x49c>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV2P5>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV4>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&clkc_pll CLKID_GP0_PLL>,
+ <&clkc_pll CLKID_MPLL0>,
+ <&clkc_pll CLKID_MPLL1>,
+ <&clkc_pll CLKID_MPLL2>,
+ <&clkc_pll CLKID_MPLL3>,
+ <&clkc_pll CLKID_HDMI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3",
+ "fclk_div4", "fclk_div5", "fclk_div7",
+ "hifi_pll", "gp0_pll", "mpll0", "mpll1",
+ "mpll2", "mpll3", "hdmi_pll", "xtal";
+ #clock-cells = <1>;
+ };
+
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,meson-s4-periphs-pinctrl";
#address-cells = <2>;
--
2.33.1
