On 04/08/2022 15:09, bchihi@xxxxxxxxxxxx wrote:
> From: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
>
> This adds the thermal zone for the mt8195.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@xxxxxxxxxxxx>
> Signed-off-by: Ben Tseng <ben.tseng@xxxxxxxxxxxx>
> Signed-off-by: Alexandre Bailon <abailon@xxxxxxxxxxxx>
> Signed-off-by: Balsam CHIHI <bchihi@xxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index cbd0401968a2..5890e688eebe 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,6 +10,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> +#include <dt-bindings/reset/mt8195-resets.h>
>
> / {
> compatible = "mediatek,mt8195";
> @@ -452,6 +453,28 @@ spi0: spi@1100a000 {
> status = "disabled";
> };
>
> + lvts_ap: thermal-sensor@1100b000 {
> + compatible = "mediatek,mt8195-lvts-ap";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
> + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
> + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
> + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
> + };
> +
> + lvts_mcu: thermal-sensor@11278000 {
> + compatible = "mediatek,mt8195-lvts-mcu";
> + #thermal-sensor-cells = <1>;
> + reg = <0 0x11278000 0 0x1000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
> + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
> + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
> + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2";
> + };
> +
> spi1: spi@11010000 {
> compatible = "mediatek,mt8195-spi",
> "mediatek,mt6765-spi";
> @@ -1106,4 +1129,92 @@ vencsys_core1: clock-controller@1b000000 {
> #clock-cells = <1>;
> };
> };
> +
> + thermal_zones: thermal-zones {
> + cpu-big1-thermal {
Does this pass dtbs_check?
Best regards,
Krzysztof
