On 27/07/2022 08:01, Chanho Park wrote: > CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2 > Lanes. > > Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
