On Wed, Jul 27, 2022 at 6:16 PM Sudeep Holla <sudeep.holla@xxxxxxx> wrote: > > On Wed, Jul 27, 2022 at 02:07:50PM +0200, Krzysztof Kozlowski wrote: > > On 27/07/2022 13:43, Anup Patel wrote: > > > We add an optional DT property riscv,timer-can-wake-cpu which if present > > > in CPU DT node then CPU timer is always powered-on and never loses context. > > > > > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > > > --- > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ > > > 1 file changed, 6 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index d632ac76532e..b60b64b4113a 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -78,6 +78,12 @@ properties: > > > - rv64imac > > > - rv64imafdc > > > > > > + riscv,timer-can-wake-cpu: > > > + type: boolean > > > + description: > > > + If present, the timer interrupt can wake up the CPU from > > > + suspend/idle state. > > > > Isn't this a property of a timer, not CPU? IOW, your timer node should > > have "wakeup-source" property. > > > > I agree on the concept that this is property of the timer and not CPU. > However we generally don't need to use wakeup-source property for timer > as we ideally use this for waking up from system sleep state and we don't > want to be running timer when we enter the state. > > > Now that's actual problem: why the RISC-V timer is bound to "riscv" > > compatible, not to dedicated timer node? How is it related to actual CPU > > (not SoC)? > > We have "always-on" property for this on arm arch timer, and I also see > "regulator-always-on" or something similar defined. So in absence of timer > node probably "local-timer-always-on" make sense ? Thoughts ? I agree. In the v1 patch, I had named it "riscv,timer-always-on" but I chose a more specific name in v2 based on comments from Samuel. I think we should use more consistent naming between ARM and RISC-V so "riscv,timer-always-on" makes more sense to me. Regards, Anup
