On Wed, Jul 27, 2022 at 05:13:01PM +0530, Anup Patel wrote: > We add an optional DT property riscv,timer-can-wake-cpu which if present > in CPU DT node then CPU timer is always powered-on and never loses context. > I don't have much idea on idle states on RISC-V but associating this property in just CPU node seems like not so good idea. This will be applicable for all CPU idle states which means you can't use this even if one of the deepest idle state switches off the timer. We have local-timer-stop in each idle states node. IIRC RISC-V uses the binding which is now not arm specific[0] and IIRC you moved the binding yourself. Any reason why not can't be used and any specific reason for needing this extra property. [0] Documentation/devicetree/bindings/cpu/idle-states.yaml -- Regards, Sudeep
