Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list

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Subject: Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Date: Wed, 27 Jul 2022 10:51:53 +0200
Cc: Anup Patel <anup@xxxxxxxxxxxxxx>, linux-renesas-soc@xxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, linux-riscv@xxxxxxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, Prabhakar <prabhakar.csengg@xxxxxxxxx>, Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
In-reply-to: <20220726180623.1668-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0

On 26/07/2022 20:06, Lad Prabhakar wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
> 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>


Best regards,
Krzysztof

References:
- [PATCH 0/6] Add support for Renesas RZ/Five SoC
  - From: Lad Prabhakar
- [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
  - From: Lad Prabhakar

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