On 26/07/2022 19:25, Conor.Dooley@xxxxxxxxxxxxx wrote: > Hey, > Saw your other binding patches coming in earlier & wondered if > this would show up today ;) > > On 26/07/2022 19:06, Lad Prabhakar wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP >> Single). >> >> Below is the list of IP blocks added in the initial SoC DTSI which can be >> used to boot via initramfs on RZ/Five SMARC EVK: >> - AX45MP CPU >> - CPG >> - PINCTRL >> - PLIC >> - SCIF0 >> - SYSC >> >> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> >> --- >> arch/riscv/boot/dts/Makefile | 1 + >> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++ > > Missing files? Where is your Makefile for this directory? > Or the board dts? > > Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :( > FWIW, it breaks the dts build too even disabled b/c of the missing Makefile. Thanks, Conor.
