This patch adds dt-binding documents for mt8192 and mt8195 thermal controllers. Signed-off-by: Alexandre Bailon <abailon@xxxxxxxxxxxx> Signed-off-by: Balsam CHIHI <bchihi@xxxxxxxxxxxx> --- .../thermal/mediatek,mt8192-lvts.yaml | 73 ++++++++++++++++++ .../thermal/mediatek,mt8195-lvts.yaml | 75 +++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml diff --git a/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml new file mode 100644 index 000000000000..8c5a02eb97c5 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,mt8192-lvts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang <ethan.chang@xxxxxxxxxxxx> + - Ben Tseng <ben.tseng@xxxxxxxxxxxx> + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + + "#thermal-sensor-cells": + const: 1 + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: SW reset HW AP/MCU domain for clean temporary data when HW initialization and resume. + + nvmem-cells: + items: + - description: LVTS calibration data for thermal sensors + + nvmem-cell-names: + items: + - const: lvts_calib_data + +required: + - compatible + - '#thermal-sensor-cells' + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/thermal/thermal.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8192-clk.h> + #include <dt-bindings/reset/mt8192-resets.h> + + lvtsmcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x400>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_THERM>; + resets = <&infracfg_ao MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data>; + nvmem-cell-names = "lvts_calib_data"; + }; + +... diff --git a/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml b/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml new file mode 100644 index 000000000000..6b0b53a33272 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,mt8195-lvts.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,mt8195-lvts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang <ethan.chang@xxxxxxxxxxxx> + - Ben Tseng <ben.tseng@xxxxxxxxxxxx> + +properties: + compatible: + enum: + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + + "#thermal-sensor-cells": + const: 1 + + reg: + maxItems: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: SW reset HW AP/MCU domain for clean temporary data when HW initialization and resume. + + nvmem-cells: + items: + - description: LVTS calibration data 1 for thermal sensors + - description: LVTS calibration data 2 for thermal sensors + + nvmem-cell-names: + items: + - const: lvts_calib_data1 + - const: lvts_calib_data2 + +required: + - compatible + - '#thermal-sensor-cells' + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/thermal/thermal.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/reset/mt8195-resets.h> + + lvtsmcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x400>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2"; + }; + +... -- 2.34.1
