Il 25/07/22 06:21, Chen-Yu Tsai ha scritto:
On Thu, Jul 21, 2022 at 10:50 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote:MT8195 features a SCP like some other older SoCs, and Cherry uses it for various tasks. Add the required pin configuration and DMA pool and enable the node. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index fcc600674339..feebbe367e93 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -104,6 +104,18 @@ usb_vbus: regulator-5v0-usb-vbus { enable-active-high; regulator-always-on; }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + }; }; &i2c0 { @@ -600,6 +612,14 @@ pins-low-power-pupd { }; }; + scp_pins: scp-default-pins { + pins-vreq { + pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>; + bias-disable; + input-enable; + }; + }; + spi0_pins: spi0-default-pins { pins-cs-mosi-clk { pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, @@ -643,6 +663,14 @@ &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; +&scp { + status = "okay"; + + memory-region = <&scp_mem>; + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>;firmware-name = "mediatek/mt8195/scp.img";
My intention was to actually add this line here. I must've erroneously dropped it during cleanup/rebase...
Or maybe this should be added to the base mt8195.dtsi? The entry for mt8192 was added to mt8192-asurada.dtsi though. Tinghan, could you ask internally whether the SCP firmware should be tied to the SoC or the projects involving the SoC?
In my opinion, even if that may be tied to the SoCs, we should still declare it in the machine(/platform) devicetree as (even if *luckily* this is not the case on Chromebooks), firmwares may be signed with a OEM key and may differ just for that. I'll send a v3 with that fix ASAP. Cheers, Angelo
Thanks ChenYu+}; + &spi0 { status = "okay"; -- 2.35.1
