On 20/07/2022 23:30, Frank Li wrote: > imx mu support generate irq by write a register. > provide msi controller support so other driver > can use it by standard msi interface. Please start sentences with capital letter. Unfortunately I don't understand the sentences. Please describe shortly the hardware. > > Signed-off-by: Frank Li <Frank.Li@xxxxxxx> > --- > .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > new file mode 100644 > index 0000000000000..e125294243af3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX Messaging Unit (MU) work as msi controller > + > +maintainers: > + - Frank Li <Frank.Li@xxxxxxx> > + > +description: | > + The Messaging Unit module enables two processors within the SoC to > + communicate and coordinate by passing messages (e.g. data, status > + and control) through the MU interface. The MU also provides the ability > + for one processor to signal the other processor using interrupts. > + > + Because the MU manages the messaging between processors, the MU uses > + different clocks (from each side of the different peripheral buses). > + Therefore, the MU must synchronize the accesses from one side to the > + other. The MU accomplishes synchronization using two sets of matching > + registers (Processor A-facing, Processor B-facing). > + > + MU can work as msi interrupt controller to do doorbell > + > +allOf: > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx6sx-mu-msi > + - fsl,imx7ulp-mu-msi > + - fsl,imx8ulp-mu-msi > + - fsl,imx8ulp-mu-msi-s4 > + > + reg: > + minItems: 2 Not minItems but maxItems in general, but anyway you need to actually list and describe the items (and then skip min/max) > + > + reg-names: > + items: > + - const: a > + - const: b > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 2 and here you correctly use maxItems, so why min in reg? Anyway, instead you need to list and describe the items. Actually I asked you this last time about interrupts, so you ignored that comment. > + > + power-domain-names: > + items: > + - const: a > + - const: b > + > + interrupt-controller: true > + > + msi-controller: true > + > +required: > + - compatible > + - reg > + - interrupts > + - msi-controller > + - interrupt-controller Why different order than used in properties? Best regards, Krzysztof
