Hi Biju, On Fri, Jul 22, 2022 at 08:19:23PM +0100, Biju Das wrote: > The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It > can operate in DSI mode, with up to four data lanes. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> > Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > v3->v4: > * No change. > v2->v3: > * Added Rb tag from Geert and Laurent > * Fixed the typo "Receive" -> "transmit" > * Added accepible values for data-lanes > * Sorted Header file in the example > * Added SoC specific compaible along with generic one. > v1->v2: > * Added full path for dsi-controller.yaml > * Modeled DSI + D-PHY as single block and updated reg property > * Fixed typo D_PHY->D-PHY > * Updated description > * Added interrupts and interrupt-names and updated the example > RFC->v1: > * Added a ref to dsi-controller.yaml. > RFC:- > * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-22-biju.das.jz@xxxxxxxxxxxxxx/ > --- > .../bindings/display/bridge/renesas,dsi.yaml | 182 ++++++++++++++++++ > 1 file changed, 182 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > new file mode 100644 > index 000000000000..131d5b63ec4f > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -0,0 +1,182 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/G2L MIPI DSI Encoder > + > +maintainers: > + - Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > + > +description: | > + This binding describes the MIPI DSI encoder embedded in the Renesas > + RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with > + up to four data lanes. > + > +allOf: > + - $ref: /schemas/display/dsi-controller.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} > + - const: renesas,rzg2l-mipi-dsi > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: Sequence operation channel 0 interrupt > + - description: Sequence operation channel 1 interrupt > + - description: Video-Input operation channel 1 interrupt > + - description: DSI Packet Receive interrupt > + - description: DSI Fatal Error interrupt > + - description: DSI D-PHY PPI interrupt > + - description: Debug interrupt This is an awful lot of interrupts. Is this really individual interrupts or status bits in a single interrupt? If it is the latter then there should be only one interrupt defined. Note: I looked at the driver, but it does not use interrupt so it did not answer my question. Sam
