RE: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding

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Hi Krzysztof Kozlowski,

Thanks for the feedback.

> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
> 
> On 18/07/2022 15:13, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
> >> POEG binding
> >>
> >> On 15/07/2022 12:17, Biju Das wrote:
> >>> Hi Krzysztof Kozlowski,
> >>>
> >>> Thanks for the feedback.
> >>>
> >>>> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
> >>>> POEG binding
> >>>>
> >>>> On 13/07/2022 15:55, Biju Das wrote:
> >>>>> Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> >>>> (POEG).
> >>>>>
> >>>>> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >>>>> ---
> >>>>> REF->v1:
> >>>>>  * Modelled as pincontrol as most of its configuration is intended
> >>>>> to
> >>>> be
> >>>>>    static.
> >>>>>  * Updated reg size in example.
> >>>>> ---
> >>>>>  .../bindings/pinctrl/renesas,rzg2l-poeg.yaml  | 65
> >>>>> +++++++++++++++++++
> >>>>>  1 file changed, 65 insertions(+)
> >>>>>  create mode 100644
> >>>>> Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >>>>>
> >>>>> diff --git
> >>>>> a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> >>>>> l
> >>>>> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> >>>>> l
> >>>>> new file mode 100644
> >>>>> index 000000000000..7607dd87fa68
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg
> >>>>> +++ .y
> >>>>> +++ am
> >>>>> +++ l
> >>>>> @@ -0,0 +1,65 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> >>>>> +1.2
> >>>>> +---
> >>>>> +$id:
> >>>>> +
> >>>>> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> >>>>> +
> >>>>> +maintainers:
> >>>>> +  - Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> >>>>> +
> >>>>> +description: |
> >>>>> +  The output pins of the general PWM timer (GPT) can be disabled
> >>>>> +by using
> >>>>> +  the port output enabling function for the GPT (POEG).
> >>>>> +Specifically,
> >>>>> +  either of the following ways can be used.
> >>>>> +  * Input level detection of the GTETRGA to GTETRGD pins.
> >>>>> +  * Output-disable request from the GPT.
> >>>>
> >>>> Shouldn't this all be part of GPT? Is this a real separate device
> >>>> in the SoC?
> >>>
> >>> No, It is separate IP block, having its own register block,
> >>> interrupts
> >> and resets.
> >>>
> >>> Please see RFC discussion here[1]
> >>>
> >>> [1]
> >>>
> >>>>
> >>>>> +  * Register settings.
> >>>>
> >>>> This is confusing... so you can use POEG to mess up registers of
> >>>> GPT independently, so GPT does not know it?
> >>>
> >>> POEG does not mess up registers of GPT. It is basically for
> protection.
> >>>
> >>> Using POEG register, it is possible to disable GPT output without
> >>> the
> >> knowledge of GPT, after configuring the Output disable source select
> >> in the GTINTAD (General PWM Timer Interrupt Output Setting Register)
> >> register present in GPT.
> >>
> >> Then what does it mean:
> >> "...following ways can be used. Register settings."
> >> I cannot parse it.
> >
> > Threre 3 methods mentioned in chapter 19.3 of RZ/G2L HW manual for
> Output-Disable Control Operation.
> > "Register settings" referred to the 3rd method as mentioned below.
> >
> > 19.3 Output-Disable Control Operation
> > The output of the GTIOCxA and GTIOCxB pins can be disabled when any of
> the following conditions are satisfied.
> >
> > 1) Input level or edge detection of the GTETRGn pins
> > 	When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
> >
> > 2) Output-disable request from the GPT When POEGGn.IOCE is 1, the
> > POEGGn.IOCF flag is set to 1.
> > The output-disable requests enabled by GRPDTE, GRPABH, and GRPABL bits
> > of the GTINTAD register in the GPT are applied to the group selected
> by GRP[1:0] bits of the GTINTAD register.
> >
> > 3) SSF bit setting
> > When POEGGn.SSF is set to 1.
> >
> > The state of the GTIOCxA and the GTIOCxB pins when the output is
> disabled is controlled by the GPT module.
> >
> > Please let me know if you need any info.
> 
> Yes, more info is needed in your patch. The "...following ways can be
> used. (...) Register settings." does not explain anything.

Ok will update bindings with POEGGn.SSF in "Register settings" section to make it clear.

Cheers,
Biju






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