On 04/07/2022 13:15, Conor Dooley wrote: > Hey all, > I know I have not sat on the RFC I sent about the aux. bus parts > for too long, but figured I'd just send the whole thing anyway to all > lists etc. Hey Stephen, Any comments on the clk/auxdev side of this series? Thanks, Conor. > > Kinda two things happening in this series, but I sent it together to > ensure the second part would apply correctly. > > The first is the reset controller that I promised after discovering the > issue triggered by CONFIG_PM & the phy not coming up correctly. I have > now removed all the messing with resets from clock enable/disable > functions & now use the aux bus to set up a reset controller driver. > Since I needed something to test it, I hooked up the reset for the > Cadence MACB on PolarFire SoC. This has been split into a second series > for v2: > https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@xxxxxxxxxxxxx/ > > The second part adds rate control for the MSS PLL clock, followed by > some simplifications to the driver & conversions of some custom structs > to the corresponding structs in the framework. > > Thanks, > Conor. > > Changes since v1: > - split off the net patches > - clk: actually pass the spinlock to the converted dividers & gates > - reset: added a spinlock around RMW access to registers > - reset: switched to BIT(i) macros > - reset: used local copies of some variables as pointed out by Philipp > - reset: dropped the success printout > > Conor Dooley (12): > dt-bindings: clk: microchip: mpfs: add reset controller support > clk: microchip: mpfs: add reset controller > reset: add polarfire soc reset support > MAINTAINERS: add polarfire soc reset controller > riscv: dts: microchip: add mpfs specific macb reset support > clk: microchip: mpfs: add module_authors entries > clk: microchip: mpfs: add MSS pll's set & round rate > clk: microchip: mpfs: move id & offset out of clock structs > clk: microchip: mpfs: simplify control reg access > clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() > clk: microchip: mpfs: convert cfg_clk to clk_divider > clk: microchip: mpfs: convert periph_clk to clk_gate > > .../bindings/clock/microchip,mpfs.yaml | 17 +- > MAINTAINERS | 1 + > arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +- > drivers/clk/microchip/Kconfig | 1 + > drivers/clk/microchip/clk-mpfs.c | 379 +++++++++--------- > drivers/reset/Kconfig | 7 + > drivers/reset/Makefile | 2 +- > drivers/reset/reset-mpfs.c | 157 ++++++++ > include/soc/microchip/mpfs.h | 8 + > 9 files changed, 386 insertions(+), 193 deletions(-) > create mode 100644 drivers/reset/reset-mpfs.c > > > base-commit: b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3
