Hi Sakari, On Sun 17 Jul 22, 11:37, Sakari Ailus wrote: > Hi Paul, > > On Mon, Jul 04, 2022 at 07:35:18PM +0200, Paul Kocialkowski wrote: > > This introduces YAML bindings documentation for the Allwinner A31 Image > > Signal Processor (ISP). > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > --- > > .../media/allwinner,sun6i-a31-isp.yaml | 97 +++++++++++++++++++ > > 1 file changed, 97 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > new file mode 100644 > > index 000000000000..2fda6e05e16c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml > > @@ -0,0 +1,97 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-isp.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Allwinner A31 Image Signal Processor Driver (ISP) Device Tree Bindings > > + > > +maintainers: > > + - Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> > > + > > +properties: > > + compatible: > > + enum: > > + - allwinner,sun6i-a31-isp > > + - allwinner,sun8i-v3s-isp > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Bus Clock > > + - description: Module Clock > > + - description: DRAM Clock > > + > > + clock-names: > > + items: > > + - const: bus > > + - const: mod > > + - const: ram > > + > > + resets: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: CSI0 input port > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: CSI1 input port > > Do both support a single PHY with a single data only? If multiple data lanes > are supported, please require data-lanes property (on endpoint). There's actually no PHY involved here: the ISP drivers gets its video stream from these CSI controllers which are the ones interfacing with a MIPI CSI-2 receiver (on A31/V3 it uses an external D-PHY, on A83T the D-PHY is collocated with the controller). So I think the data-lanes property is not relevant here. What do you think? Cheers, Paul > > + > > + anyOf: > > + - required: > > + - port@0 > > + - required: > > + - port@1 > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + - resets > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/sun8i-v3s-ccu.h> > > + #include <dt-bindings/reset/sun8i-v3s-ccu.h> > > + > > + isp: isp@1cb8000 { > > + compatible = "allwinner,sun8i-v3s-isp"; > > + reg = <0x01cb8000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>, > > + <&ccu CLK_DRAM_CSI>; > > + clock-names = "bus", "mod", "ram"; > > + resets = <&ccu RST_BUS_CSI>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + > > + isp_in_csi0: endpoint { > > + remote-endpoint = <&csi0_out_isp>; > > + }; > > + }; > > + }; > > + }; > > + > > +... > > -- > Sakari Ailus -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com
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