This is a first stab at adding serdes support on the LS1088A. Linux hangs
around when the serdes is initialized if the si5341 is enabled, so it's
commented out. I also discovered that I have too old MC firmware to
reconfigure the phy interface mode. Consider all the LS1088A parts of
this series to be untested, but hopefully they can be a good starting
point.
Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx>
---
(no changes since v1)
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 1bfbce69cc8b..5875709f7f8b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -15,12 +15,59 @@
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clocks {
+ si5341_xtal: clock-48mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+ };
+
+ ovdd: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "ovdd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ dvdd: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+};
+
+&serdes1 {
+ //clocks = <&si5341 0 8>, <&si5341 0 9>;
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ status = "okay";
+};
+
+&dpmac1 {
+ phys = <&serdes1 1>;
};
&dpmac2 {
phy-handle = <&mdio2_aquantia_phy>;
phy-connection-type = "10gbase-r";
pcs-handle = <&pcs2>;
+ phys = <&serdes1 0>;
};
&dpmac3 {
@@ -28,6 +75,7 @@ &dpmac3 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_0>;
+ phys = <&serdes1 3>;
};
&dpmac4 {
@@ -35,6 +83,7 @@ &dpmac4 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
+ phys = <&serdes1 3>;
};
&dpmac5 {
@@ -42,6 +91,7 @@ &dpmac5 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_2>;
+ phys = <&serdes1 3>;
};
&dpmac6 {
@@ -49,6 +99,7 @@ &dpmac6 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_3>;
+ phys = <&serdes1 3>;
};
&dpmac7 {
@@ -56,6 +107,7 @@ &dpmac7 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_0>;
+ phys = <&serdes1 2>;
};
&dpmac8 {
@@ -63,6 +115,7 @@ &dpmac8 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_1>;
+ phys = <&serdes1 2>;
};
&dpmac9 {
@@ -70,6 +123,7 @@ &dpmac9 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_2>;
+ phys = <&serdes1 2>;
};
&dpmac10 {
@@ -77,6 +131,7 @@ &dpmac10 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_3>;
+ phys = <&serdes1 2>;
};
&emdio1 {
@@ -142,6 +197,38 @@ i2c-switch@77 {
#address-cells = <1>;
#size-cells = <0>;
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+
+ si5341: clock-generator@74 {
+ #address-cells = <1>;
+ #clock-cells = <2>;
+ #size-cells = <0>;
+ compatible = "silabs,si5341";
+ reg = <0x74>;
+ clocks = <&si5341_xtal>;
+ clock-names = "xtal";
+ vdd-supply = <&ovdd>;
+ vdda-supply = <&dvdd>;
+ vddo8-supply = <&ovdd>;
+ vddo9-supply = <&ovdd>;
+ silabs,iovdd-33;
+ status = "disabled";
+
+ out@8 {
+ reg = <8>;
+ silabs,format = <1>;
+ };
+
+ out@9 {
+ reg = <9>;
+ silabs,format = <1>;
+ };
+ };
+ };
+
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.1.1320.gc452695387.dirty
