On 07-07-22, 01:52, Vinod Koul wrote: > On 06-07-22, 17:10, Wangseok Lee wrote: >> On 05-07-22, 15:30, Vinod Koul wrote: >> > On 14-06-22, 10:34, Wangseok Lee wrote: >> >> Add support Axis, ARTPEC-8 SoC. >> >> ARTPEC-8 is the SoC platform of Axis Communications. >> >> This is based on arm64 and support GEN4 & 2lane. >> >> This driver provides PHY interface for ARTPEC-8 SoC PCIe controller, >> >> based on Samsung PCIe PHY IP. >> >> >> >> Signed-off-by: Wangseok Lee <wangseok.lee@xxxxxxxxxxx> >> >> Signed-off-by: Jaeho Cho <jaeho79.cho@xxxxxxxxxxx> >> >> --- >> >> v2->v3 : >> >> -remove unnecessary indentation >> >> -redefine local struct to statis const >> >> -add static const to struct that requires static const definition >> >> -remove wrappers on writel and readl >> >> >> >> v1->v2 : >> >> -change folder name of phy driver to axis from artpec >> >> --- >> >> drivers/phy/Kconfig | 1 + >> >> drivers/phy/Makefile | 1 + >> >> drivers/phy/axis/Kconfig | 9 + >> >> drivers/phy/axis/Makefile | 2 + >> >> drivers/phy/axis/phy-artpec8-pcie.c | 776 ++++++++++++++++++++++++++++++++++++ >> >> 5 files changed, 789 insertions(+) >> >> create mode 100644 drivers/phy/axis/Kconfig >> >> create mode 100644 drivers/phy/axis/Makefile >> >> create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c >> >> >> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig >> >> index 300b0f2..92b8232 100644 >> >> --- a/drivers/phy/Kconfig >> >> +++ b/drivers/phy/Kconfig >> >> @@ -73,6 +73,7 @@ config PHY_CAN_TRANSCEIVER >> >> >> >> source "drivers/phy/allwinner/Kconfig" >> >> source "drivers/phy/amlogic/Kconfig" >> >> +source "drivers/phy/axis/Kconfig" >> >> source "drivers/phy/broadcom/Kconfig" >> >> source "drivers/phy/cadence/Kconfig" >> >> source "drivers/phy/freescale/Kconfig" >> >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile >> >> index 01e9eff..808c055e 100644 >> >> --- a/drivers/phy/Makefile >> >> +++ b/drivers/phy/Makefile >> >> @@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o >> >> obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o >> >> obj-y += allwinner/ \ >> >> amlogic/ \ >> >> + axis/ \ >> >> broadcom/ \ >> >> cadence/ \ >> >> freescale/ \ >> >> diff --git a/drivers/phy/axis/Kconfig b/drivers/phy/axis/Kconfig >> >> new file mode 100644 >> >> index 0000000..7198b93 >> >> --- /dev/null >> >> +++ b/drivers/phy/axis/Kconfig >> >> @@ -0,0 +1,9 @@ >> >> +config PHY_ARTPEC8_PCIE >> >> + bool "ARTPEC-8 PCIe PHY driver" >> >> + depends on OF && (ARCH_ARTPEC8 || COMPILE_TEST) >> >> + select GENERIC_PHY >> >> + help >> >> + Enable PCIe PHY support for ARTPEC-8 SoC. >> >> + This driver provides PHY interface for ARTPEC-8 SoC >> >> + PCIe controller. >> >> + This is based on Samsung PCIe PHY IP. >> > >> > How different is it from SS IP and why should it not be under >> > phy/samsung/ then? >> > >> >> SoC platform is completely different from exynos platform and different >> from exynos PCIe PHY. So the overall sysreg configuration is different >> and register map is also different. The reset method and type of PHY for >> initialization are different. This is not a driver that supports Samsung >> SoC platform, but this PHY driver that supports only Axis, Artpec-8 >> platforms, so it is not added to phy/samsung. > > SoC is a moot point. If the IP block is same then we should try to reuse > the existing phy driver, modifications to current driver to support your > changes should be fine... > > Is that feasible? > > -- > ~Vinod Sorry for late reply. Above all, the IP blocks of phy-exynos-pcie.c and artpec8's pcie phy are different. As a result, the H/W architecture and operation sequence is very different. So it is very difficult to merge into a exynos pcie file. If possible, we would like to proceed with a new file. Is that possible? Best regards, Wangseok Lee
