On Wed, Jul 13, 2022 at 03:13:38PM +0200, Johan Hovold wrote:
> The two single-port SC8280XP USB controllers do not have an hs_phy_irq
> interrupt. Instead they have a pwr_event interrupt which is distinct
> from the former and not yet supported by the driver.
>
> Fix the USB node interrupt names so that they match the devicetree
> binding.
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 45cc7d714fd2..4a7aa9992f3a 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1875,8 +1875,10 @@ usb_0: usb@a6f8800 {
> <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
> - "dm_hs_phy_irq", "ss_phy_irq";
> + interrupt-names = "pwr_event",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
>
> power-domains = <&gcc USB30_PRIM_GDSC>;
>
> @@ -1925,8 +1927,10 @@ usb_1: usb@a8f8800 {
> <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
> <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
> - "dm_hs_phy_irq", "ss_phy_irq";
> + interrupt-names = "pwr_event",
> + "dp_hs_phy_irq",
> + "dm_hs_phy_irq",
> + "ss_phy_irq";
For this specific change to pwr_event:
Reviewed-by: Andrew Halaney <ahalaney@xxxxxxxxxx>
That being said, I was reviewing this against the (fairly old)
downstream release I have, and the IRQs defined there look like this:
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
The part I want to highlight is that the "pwr_event" irq downstream maps
to <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, but the current upstream
devicetree I'm looking at has it mapped to <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>
Do you happen to have any source you can also check to confirm if this
is a bug or not?
Thanks,
Andrew
>
> power-domains = <&gcc USB30_SEC_GDSC>;
>
> --
> 2.35.1
>
