On Mon, 4 Jul 2022 at 16:35, Robert Marko <robimarko@xxxxxxxxx> wrote: > > Commit "mmc: sdhci-msm: Reset GCC_SDCC_BCR register for SDHC" added > support for utilizing a hardware reset and parsing it from DT, however > the bindings were not updated along with it. > > So, document the usage of "resets" property with the limit of only one > item. > > Signed-off-by: Robert Marko <robimarko@xxxxxxxxx> Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > index 31a3ce208e1a..ca8814a80443 100644 > --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml > @@ -116,6 +116,9 @@ properties: > description: > Should specify pin control groups used for this controller. > > + resets: > + maxItems: 1 > + > qcom,ddr-config: > $ref: /schemas/types.yaml#/definitions/uint32 > description: platform specific settings for DDR_CONFIG reg. > -- > 2.36.1 >
