On Mon, 11 Jul 2022 at 20:44, Conor Dooley <mail@xxxxxxxxxxx> wrote:
>
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> The JH7100 has a 32 bit monitor core that is missing from the device
> tree. Add it (and its cpu-map entry) to more accurately reflect the
> actual topology of the SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
Thanks!
/Emil
> ---
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index c617a61e26e2..92fce5b66d3d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -67,6 +67,23 @@ cpu1_intc: interrupt-controller {
> };
> };
>
> + E24: cpu@2 {
> + compatible = "sifive,e24", "riscv";
> + reg = <2>;
> + device_type = "cpu";
> + i-cache-block-size = <32>;
> + i-cache-sets = <256>;
> + i-cache-size = <16384>;
> + riscv,isa = "rv32imafc";
> + status = "disabled";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> cpu-map {
> cluster0 {
> core0 {
> @@ -76,6 +93,10 @@ core0 {
> core1 {
> cpu = <&U74_1>;
> };
> +
> + core2 {
> + cpu = <&E24>;
> + };
> };
> };
> };
> --
> 2.37.0
>
