Quoting Cixi Geng (2022-05-05 03:14:33)
> diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c
> new file mode 100644
> index 000000000000..53ed58de61cd
> --- /dev/null
> +++ b/drivers/clk/sprd/ums512-clk.c
> @@ -0,0 +1,2199 @@
> +// SPDX-License-Identifier: GPL
Please pick an appropriate license.
WARNING: 'SPDX-License-Identifier: GPL' is not supported in LICENSES/...
#49: FILE: drivers/clk/sprd/ums512-clk.c:1:
+// SPDX-License-Identifier: GPL
> +/*
> + * Unisoc UMS512 clock driver
> + *
> + * Copyright (C) 2022 Unisoc, Inc.
> + * Author: Xiaolong Zhang <xiaolong.zhang@xxxxxxxxxx>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/clock/sprd,ums512-clk.h>
> +
> +#include "common.h"
> +#include "composite.h"
> +#include "div.h"
> +#include "gate.h"
> +#include "mux.h"
> +#include "pll.h"
> +
> +#define UMS512_MUX_FLAG \
> + (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
Why do we need nocache?
> +
> +/* pll gate clock */
> +/* some pll clocks configure CLK_IGNORE_UNUSED because hw dvfs does not call
> + * clock interface. hw dvfs can not gate the pll clock.
> + */
> +static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0);
[...]
> + .hw_clks = &ums512_pmu_gate_hws,
> +};
> +
> +/* pll clock at g0 */
> +static const u64 itable_dpll0[7] = {6, 0, 0,
Please put space after '{' and before '}'
> + 1173000000ULL, 1475000000ULL,
> + 1855000000ULL, 1866000000ULL};
> +
[...]
> +
> +static int ums512_clk_probe(struct platform_device *pdev)
> +{
> + const struct sprd_clk_desc *desc;
> +
> + desc = device_get_match_data(&pdev->dev);
> + if (!desc)
> + return -ENODEV;
> +
> + sprd_clk_regmap_init(pdev, desc);
Check for error please
> +
> + return sprd_clk_probe(&pdev->dev, desc->hw_clks);
> +}
> +
