How to correctly define memory range of PCIe config space

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hello!

Together with Mauri we are working on extending pci-mvebu.c driver to
support Orion PCIe controllers as these controllers are same as mvebu
controller.

There is just one big difference: Config space access on Orion is
different. mvebu uses classic Intel CFC/CF8 registers for indirect
config space access but Orion has direct memory mapped config space.
So Orion DTS files need to have this memory range for config space and
pci-mvebu.c driver have to read this range from DTS and properly map it.

So my question is: How to properly define config space range in device
tree file? In which device tree property and in which format? Please
note that this memory range of config space is PCIe root port specific
and it requires its own MBUS_ID() like memory range of PCIe MEM and PCIe
IO mapping. Please look e.g. at armada-385.dtsi how are MBUS_ID() used:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/armada-385.dtsi

Krzysztof, would you be able to help with proper definition of this
property, so it would be fine also for schema checkers or other
automatic testing tools?



[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux