Move schema for qcom,sc7280-mdss from dpu-sc7280.yaml to mdss.yaml so
that the dpu file describes only the DPU schema.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
.../bindings/display/msm/dpu-sc7280.yaml | 148 +++++-------------
.../devicetree/bindings/display/msm/mdss.yaml | 19 +++
2 files changed, 57 insertions(+), 110 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
index f427eec3d3a4..349a454099ad 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
@@ -10,149 +10,77 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@xxxxxxxxxxx>
description: |
- Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
- sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
- bindings of MDSS and DPU are mentioned for SC7280.
+ Device tree bindings for the DPU display controller for SC7280 target.
properties:
compatible:
- const: qcom,sc7280-mdss
+ const: qcom,sc7280-dpu
reg:
- maxItems: 1
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
reg-names:
- const: mdss
-
- power-domains:
- maxItems: 1
+ items:
+ - const: mdp
+ - const: vbif
clocks:
items:
- - description: Display AHB clock from gcc
- - description: Display AHB clock from dispcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
- description: Display core clock
+ - description: Display vsync clock
clock-names:
items:
+ - const: bus
+ - const: nrt_bus
- const: iface
- - const: ahb
+ - const: lut
- const: core
+ - const: vsync
interrupts:
maxItems: 1
- interrupt-controller: true
-
- "#address-cells": true
-
- "#size-cells": true
-
- "#interrupt-cells":
- const: 1
-
- iommus:
- items:
- - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
-
- ranges: true
-
- interconnects:
- items:
- - description: Interconnect path specifying the port ids for data bus
-
- interconnect-names:
- const: mdp0-mem
+ power-domains:
+ maxItems: 1
- resets:
- items:
- - description: MDSS_CORE reset
+ operating-points-v2: true
-patternProperties:
- "^display-controller@[0-9a-f]+$":
- type: object
- description: Node containing the properties of DPU.
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
properties:
- compatible:
- const: qcom,sc7280-dpu
-
- reg:
- items:
- - description: Address offset and size for mdp register set
- - description: Address offset and size for vbif register set
-
- reg-names:
- items:
- - const: mdp
- - const: vbif
-
- clocks:
- items:
- - description: Display hf axi clock
- - description: Display sf axi clock
- - description: Display ahb clock
- - description: Display lut clock
- - description: Display core clock
- - description: Display vsync clock
-
- clock-names:
- items:
- - const: bus
- - const: nrt_bus
- - const: iface
- - const: lut
- - const: core
- - const: vsync
-
- interrupts:
- maxItems: 1
-
- power-domains:
- maxItems: 1
-
- operating-points-v2: true
-
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- description: |
- Contains the list of output ports from DPU device. These ports
- connect to interfaces that are external to the DPU hardware,
- such as DSI, DP etc. Each output port contains an endpoint that
- describes how it is connected to an external interface.
-
- properties:
- port@0:
- $ref: /schemas/graph.yaml#/properties/port
- description: DPU_INTF1 (DSI)
-
- port@1:
- $ref: /schemas/graph.yaml#/properties/port
- description: DPU_INTF5 (EDP)
-
- required:
- - port@0
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI)
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF5 (EDP)
required:
- - compatible
- - reg
- - reg-names
- - clocks
- - interrupts
- - power-domains
- - operating-points-v2
- - ports
+ - port@0
required:
- compatible
- reg
- reg-names
- - power-domains
- clocks
- interrupts
- - interrupt-controller
- - iommus
- - ranges
+ - power-domains
+ - operating-points-v2
+ - ports
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/display/msm/mdss.yaml b/Documentation/devicetree/bindings/display/msm/mdss.yaml
index 98f1f2501291..b1c7193417be 100644
--- a/Documentation/devicetree/bindings/display/msm/mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdss.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,sc7180-mdss
+ - qcom,sc7280-mdss
- qcom,sdm845-mdss
- qcom,mdss
@@ -167,6 +168,7 @@ allOf:
contains:
enum:
- qcom,sc7180-mdss
+ - qcom,sc7280-mdss
then:
properties:
clocks:
@@ -206,6 +208,7 @@ patternProperties:
"^display-controller@(0|[1-9a-f][0-9a-f]*)$":
oneOf:
- $ref: dpu-sc7180.yaml
+ - $ref: dpu-sc7280.yaml
- $ref: dpu-sdm845.yaml
"^displayport-controller@(0|[1-9a-f][0-9a-f]*)$":
@@ -229,6 +232,14 @@ patternProperties:
- $ref: dsi-phy-10nm.yaml#
- $ref: dsi-phy-7nm.yaml#
+ "^edp@(0|[1-9a-f][0-9a-f]*)$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,sc7280-edp
+ - qcom,sc8180x-edp
+
"^hdmi-phy@(0|[1-9a-f][0-9a-f]*)$":
oneOf:
- $ref: /schemas/phy/qcom,hdmi-phy-qmp.yaml#
@@ -237,6 +248,14 @@ patternProperties:
"^hdmi-tx@(0|[1-9a-f][0-9a-f]*)$":
$ref: hdmi.yaml#
+ "^phy@(0|[1-9a-f][0-9a-f]*)$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - qcom,sc7280-dsi-phy-7nm
+ - qcom,sc7280-edp-phy
+
additionalProperties: false
examples:
--
2.35.1
