Add support for PCIe controllers that operate in the endpoint mode
in tegra234 chipset.
Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
---
V4:
* Rebased on top of previous patch
V3:
* New patch in this series
.../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 123 +++++++++++++++++-
1 file changed, 117 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
index 98e2d40e876b..cffe8e8bec94 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
@@ -18,6 +18,7 @@ description: |
in root port mode or endpoint mode but one at a time.
On Tegra194, controllers C0, C4 and C5 support endpoint mode.
+ On Tegra234, controllers C5, C6, C7 and C10 support endpoint mode.
Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
operate in the endpoint mode because of the way the platform is designed.
@@ -26,6 +27,7 @@ properties:
compatible:
enum:
- nvidia,tegra194-pcie-ep
+ - nvidia,tegra234-pcie-ep
reg:
items:
@@ -96,7 +98,8 @@ properties:
A phandle to the node that controls power to the respective PCIe
controller and a specifier name for the PCIe controller.
- specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+ Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+ Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" file.
interconnects:
items:
@@ -116,17 +119,30 @@ properties:
Must contain a pair of phandle to BPMP controller node followed by
controller ID. Following are the controller IDs for each controller:
+ Tegra194
+
0: C0
1: C1
2: C2
3: C3
4: C4
5: C5
- items:
- - items:
- - description: phandle to BPMP controller node
- - description: PCIe controller ID
- maximum: 5
+
+ Tegra234
+
+ 0 : C0
+ 1 : C1
+ 2 : C2
+ 3 : C3
+ 4 : C4
+ 5 : C5
+ 6 : C6
+ 7 : C7
+ 8 : C8
+ 9 : C9
+ 10: C10
+
+ Platform constraints are described later
nvidia,aspm-cmrt-us:
description: Common Mode Restore Time for proper operation of ASPM to be
@@ -146,9 +162,47 @@ properties:
maxItems: 1
description: GPIO used to enable REFCLK to controller from the host
+ nvidia,enable-srns:
+ description: |
+ This boolean property needs to be present if the controller is configured
+ to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking).
+ NOTE:- This is applicable only for Tegra234.
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
allOf:
- $ref: /schemas/pci/pci-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra194-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - description: phandle to BPMP controller node
+ - description: PCIe controller ID
+ maximum: 5
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - description: phandle to BPMP controller node
+ - description: PCIe controller ID
+ maximum: 10
+
unevaluatedProperties: false
required:
@@ -226,3 +280,60 @@ examples:
"p2u-5", "p2u-6", "p2u-7";
};
};
+
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/gpio/tegra234-gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie-ep@141a0000 {
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
+
+ reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon
+ TEGRA234_AON_GPIO(AA, 4)
+ GPIO_ACTIVE_HIGH>;
+
+ num-lanes = <8>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+ };
--
2.17.1
