Hi Stephen,
On 6/15/2022 2:08 AM, Stephen Boyd wrote:
Quoting Matthias Kaehlcke (2022-06-14 09:51:57)
On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
driver is not supported and mark it disabled. Also to keep consistency
update lpasscore to lpass_core.
There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
isn't supported?
IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
have overlapping register ranges, so they can't be used together.
You could just say 'Disable the LPASS PIL clock by default, boards
can enable it if needed'.
For the pinctrl driver we added a "qcom,adsp-bypass-mode" property[1] to
indicate that the ADSP was being bypassed or not. Can we do the same
here and combine the device nodes that have overlapping reg properties?
[1] https://lore.kernel.org/r/1654921357-16400-2-git-send-email-quic_srivasam@xxxxxxxxxxx
Could we take up as a cleanup and take it forward:
https://lore.kernel.org/lkml/20220614153306.29339-1-quic_tdas@xxxxxxxxxxx/T/#t
--
Thanks & Regards,
Taniya Das.
