Reviewed-by: Guo Ren <guoren@xxxxxxxxxx> On Wed, Jul 6, 2022 at 6:47 AM Heiko Stuebner <heiko@xxxxxxxxx> wrote: > > The Zicbom operates on a block-size defined for the cpu-core, > which does not necessarily match other cache-sizes used. > > So add the necessary property for the system to know the core's > block-size. > > Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx> > Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d632ac76532e..873dd12f6e89 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -63,6 +63,11 @@ properties: > - riscv,sv48 > - riscv,none > > + riscv,cbom-block-size: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + The blocksize in bytes for the Zicbom cache operations. > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture > -- > 2.35.1 > -- Best Regards Guo Ren
