From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
On Wed, 29 Jun 2022 21:07:33 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
>
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
>
> [...]
Applied to dt-fixes, thanks!
[1/1] riscv: dts: microchip: hook up the mpfs' l2cache
https://git.kernel.org/conor/c/efa310ba0071
Thanks,
Conor.
