On 22/07/05 04:03PM, Krzysztof Kozlowski wrote: > On 05/07/2022 16:00, Han Xu wrote: > >> So we probably misunderstood each other... looking at the driver it also explains > >> the confusing. You encoded here register value which is pretty often wrong > >> approach. > >> > >> This should be instead meaningful value for the user of the bindings, so usually > >> using one of property units: > >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F&data=05%7C01%7Chan.xu%40nxp.com%7C8b8e3e6291c24579020308da5e8f2916%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637926266207468995%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=KHgjKLX7M8CYfJoWqpVhNdZc%2FlZhZxp6CuaPTUYgwE8%3D&reserved=0 > >> %2Fdevicetree-org%2Fdt- > >> schema%2Fblob%2Fmain%2Fdtschema%2Fschemas%2Fproperty- > >> units.yaml&data=05%7C01%7Chan.xu%40nxp.com%7C0ffe3d706e064f14382 > >> 108da5e8a5add%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6379262 > >> 45564450475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV > >> 2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Q4 > >> SfVnBN%2BQ0vYKJzRf%2FXZkCA1WGyPV9doFcb%2BLSKx4w%3D&reserved=0 > >> > >> I think you could use here clock cycles or clock phase, but then it has to be obvious > >> it is that unit. > > > > Hi Krzysztof, > > > > Let me clarify it, in the document a term "delay cell" was used to descript this register bit. > > Which document? The bindings (I cannot find it there)? Commit msg? The SoC Reference Manual. > > > Each delay cell equals "1/32 clock phase", so the unit of delay cell is clock phase. The value user need set in DT just number to define how many delay cells needed. > > Your bindings did not say this at all. I will explain all details in v2 patch. > > Best regards, > Krzysztof
