On Fri, 2022-07-01 at 14:29 -0600, Rob Herring wrote: > On Fri, Jul 01, 2022 at 02:27:59PM +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > > > > This controller is present on several mediatek hardware. Currently > > mt8195 and mt8395 have this controller without a functional > > difference, > > so only one compatible field is added. > > > > The controller can have two forms, as a normal display port and as > > an > > embedded display port. > > I'm sure you answered this before, but I'll keep asking until the > information is contained within this patch. Otherwise, I won't > remember. > Is there a h/w difference in the 2 blocks? Different registers? Why > can't you just look at what the output is connected to? > Hello Rob, Thanks for your review. Yes, it's two different hw for edp and dp and they have different registers base address. I will add this information in next version. > > > > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx> > > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx> > > --- > > .../display/mediatek/mediatek,dp.yaml | 108 > > ++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > new file mode 100644 > > index 000000000000..26047fc65e7d > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > @@ -0,0 +1,108 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml*__;Iw!!CTRNKA9wMg0ARbw!0rhwy9BSTdon0PvJuF9KabbkL9STTTnUEnTBbW_pQD_ZJP7Ziu6lhepb8fUWCnoLWHAXfmmVC6-qsI6YUpPv_qzirg$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0rhwy9BSTdon0PvJuF9KabbkL9STTTnUEnTBbW_pQD_ZJP7Ziu6lhepb8fUWCnoLWHAXfmmVC6-qsI6YUpOIsTMz8Q$ > > > > + > > +title: MediaTek Display Port Controller > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@xxxxxxxxxx> > > + - Jitao shi <jitao.shi@xxxxxxxxxxxx> > > + > > +description: | > > + Device tree bindings for the MediaTek display port and > > + embedded display port controller present on some MediaTek SoCs. > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8195-dp-tx > > + - mediatek,mt8195-edp-tx > > + > > + reg: > > + maxItems: 1 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: efuse data for display port calibration > > + > > + nvmem-cell-names: > > + const: dp_calibration_data > > + > > + power-domains: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Input endpoint of the controller, usually > > dp_intf > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Output endpoint of the controller > > + > > + required: > > + - port@0 > > + - port@1 > > + > > + data-lanes: > > This is not where data-lanes belongs. It goes in port@1 endpoint. > Look > at other users. > Do you mean I need to put "data-lanes" inside port? BRs, Bo-Chen > > + $ref: /schemas/media/video-interfaces.yaml#/properties/data- > > lanes > > Generally, not how references look in DT bindings. > > > + description: | > > + number of lanes supported by the hardware. > > + The possible values: > > + 0 - For 1 lane enabled in IP. > > + 0 1 - For 2 lanes enabled in IP. > > + 0 1 2 3 - For 4 lanes enabled in IP. > > + minItems: 1 > > + maxItems: 4 > > + > > + max-linkrate-mhz: > > + enum: [ 1620, 2700, 5400, 8100 ] > > + description: maximum link rate supported by the hardware. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - ports > > + - data-lanes > > + - max-linkrate-mhz > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + dp_tx@1c600000 { > > + compatible = "mediatek,mt8195-dp-tx"; > > + reg = <0x1c600000 0x8000>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > > + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; > > + data-lanes = <0 1 2 3>; > > + max-linkrate-mhz = <8100>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + edp_in: endpoint { > > + remote-endpoint = <&dp_intf0_out>; > > + }; > > + }; > > + port@1 { > > + reg = <1>; > > + edp_out: endpoint { > > + remote-endpoint = <&panel_in>; > > + }; > > + }; > > + }; > > + }; > > -- > > 2.18.0 > > > >
