On Fri, 26 Sep 2014 10:54:15 +0200, Gabriel FERNANDEZ said: > SSC is the technique of modulating the operating frequency of a signal > slightly to spread its radiated emissions over a range of frequencies. > This reduction in the maximum emission for a given frequency helps meet > radiated emission requirements. > These settings are applicable for PCIE with Internal clock. > + writeb_relaxed(0x69, miphy_phy->base + MIPHY_PLL_SBR_3); > + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); > + writeb_relaxed(0x3c, miphy_phy->base + MIPHY_PLL_SBR_2); > + writeb_relaxed(0x21, miphy_phy->base + MIPHY_PLL_SBR_4); > + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); > + writeb_relaxed(0x02, miphy_phy->base + MIPHY_PLL_SBR_1); > + writeb_relaxed(0x00, miphy_phy->base + MIPHY_PLL_SBR_1); I'd feel a lot better about all these magic numbers (and the triple write to SBR_1) if the Changelog or something referenced where they came from....
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