On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote: > Add two PLL clock source, they are the parent clocks of root clock > one is for 8kHz series rates, another one is for 11kHz series rates. > They are optional clocks, if there are such clocks, then driver > can switch between them for supporting more accurate rates. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx> > --- > Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
