Hi Biju,
On Fri, Jul 1, 2022 at 6:23 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -423,6 +423,24 @@ gic: interrupt-controller@44101000 {
> interrupts =
> <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
> };
> +
> + can0: can@52104000 {
> + compatible = "nxp,sja1000";
Is this block 100% compatible to the nxp,sja1000 block, or do we
need an SoC-specific compatible value?
> + reg = <0x52104000 0x800>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
According to the (old) bindings, the clock rate is specified using the
non-standard "nxp,external-clock-frequency property" (seems like both
bindings and driver can use some overhaul), and defaults to 16 MHz.
According to the RZ/N1S documentation, the CAN clock is 48 MHz?
> + status = "disabled";
> + };
> +
> + can1: can@52105000 {
> + compatible = "nxp,sja1000";
> + reg = <0x52105000 0x800>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
> + status = "disabled";
> + };
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
