On Thu, 2022-06-30 at 09:47 +0800, CK Hu wrote:
> Hi, Bo-Chen:
>
> On Mon, 2022-06-27 at 16:03 +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> >
> > This patch adds a embedded displayport driver for the MediaTek
> > mt8195
> > SoC.
> >
> > It supports the MT8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> >
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> >
> > This driver is based on an initial version by
> > Jitao shi <jitao.shi@xxxxxxxxxxxx>
> >
> > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> > ---
>
> [snip]
>
> > +
> > +static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
> > +{
> > + mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
> > +
> > + mtk_dp_write(mtk_dp, MTK_DP_0034,
> > + DA_CKM_CKTX0_EN_FORCE_EN |
> > + DA_CKM_BIAS_LPF_EN_FORCE_VAL |
> > + DA_CKM_BIAS_EN_FORCE_VAL |
> > + DA_XTP_GLB_LDO_EN_FORCE_VAL |
> > + DA_XTP_GLB_AVD10_ON_FORCE_VAL);
>
> Is this clock gating? If so, separate this to ccf driver.
>
> Regards,
> CK
>
Hello CK,
this register is inside dp hardware, so it should not move to ccf
driver.
BRs,
Bo-Chen
> > +
> > + /* Disable RX */
> > + mtk_dp_write(mtk_dp, MTK_DP_1040, 0);
> > + mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,
> > + 0x550 | BIT(FUSE_SEL_SHIFT) |
> > BIT(MEM_ISO_EN_SHIFT));
> > +}
> > +
>
>
