The RISC-V PLIC specification unfortunately allows PLIC implementations
to ignore edges seen while an edge-triggered interrupt is being handled:
Depending on the design of the device and the interrupt handler,
in between sending an interrupt request and receiving notice of its
handler’s completion, the gateway might either ignore additional
matching edges or increment a counter of pending interrupts.
Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus
it also needs to inform software about each interrupt's trigger type, so
the driver can use the right interrupt flow.
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
---
Changes in v3:
- Rebased on top of the RZ/Five patches
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index cd2b8bcaec3b..92e0f8c3eff2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -33,7 +33,7 @@ description:
it is not included in the interrupt specifier. In the second case, software
needs to know the trigger type, so it can reorder the interrupt flow to avoid
missing interrupts. This special handling is needed by at least the Renesas
- RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100).
+ RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -112,6 +112,7 @@ allOf:
contains:
enum:
- andestech,nceplic100
+ - thead,c900-plic
then:
properties:
--
2.35.1
