On Wed, Jun 29, 2022 at 12:27 PM Chanho Park <chanho61.park@xxxxxxxxxxx> wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx> While this gives a way to set up the default clock divider (which is fair) I think you should probably go the extra mile and make this clock divider a proper clock abstraction, so the driver can respect the DT standard property spi-max-frequency from Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml This actually isn't very hard: look for example in the PL111 driver, a hardware block that contains a similar internal clock divider: drivers/gpu/drm/pl111/pl111_display.c check how we define a clock from pl111_clk_div_ops. in pl111_init_clock_divider(). Then the driver probe() just grabs that clock and sets the frequency. The algorithms should be pretty much copy/paste. Yours, Linus Walleij
