Hi Chanho, On Wed, Jun 29, 2022 at 07:23:02PM +0900, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx> Reviewed-by: Andi Shyti <andi@xxxxxxxxxxx> Thanks, Andi
