> Wiadomość napisana przez Peter Geis <pgwipeout@xxxxxxxxx> w dniu 25.06.2022, o godz. 16:00: > > > The first issue you have is the TV isn't responding until the absolute > end. I suspect this is because lack on idle gaps between cec commands sent from board to tv. Maybe TV sw. can't deal with consecutive commands without any idle between them? It is interesting that disconnecting TV - so CEC line is driven only by board - rock3a still don't have any idle gaps while rock3b (and radxa 4.19 bsp) has them (very similar between 5.18mailine and 4.19 bsp). How this is possible that change I/O from m0->m1 impacts _timings_ on free hanging CEC line? > This strikes me as a signal integrity issue. Do you have an > oscilloscope (not a logic analyzer, you need voltages and ramp times) > to compare the working vs non-working signals? Check both sides of the > level shifter. Indeed - i will verify this with digital oscilloscope. Already ordered and must await week or 2 for delivery :-( My analog oscilloscope shows correct levels and slopes "seems" to be the same like in working (no memory so i can compare only visually on fuzzy screen) For me key is to understand why on rock3a there is no any idles between cec commands - even when nothing is connected to bard (so cec is only sending and nothing external impacts cec state machine)....
