Hi Geert, Thank you for the review. On Thu, Jun 9, 2022 at 10:42 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Tue, May 24, 2022 at 7:22 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > Document Renesas RZ/Five (R9A07G043) SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Thanks for your patch! > > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > > @@ -28,7 +28,10 @@ description: > > > > While the PLIC supports both edge-triggered and level-triggered interrupts, > > interrupt handlers are oblivious to this distinction and therefore it is not > > - specified in the PLIC device-tree binding. > > + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's), > > + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need > > + to specify the interrupt type as the flow for EDGE interrupts is different > > + compared to LEVEL interrupts. > > > > While the RISC-V ISA doesn't specify a memory layout for the PLIC, the > > "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that > > @@ -57,6 +60,7 @@ properties: > > - enum: > > - allwinner,sun20i-d1-plic > > - const: thead,c900-plic > > + - const: renesas-r9a07g043-plic > > renesas,r9a07g043-plic > Agreed. > > > > reg: > > maxItems: 1 > > @@ -64,8 +68,7 @@ properties: > > '#address-cells': > > const: 0 > > > > - '#interrupt-cells': > > - const: 1 > > + '#interrupt-cells': true > > > > interrupt-controller: true > > > > @@ -91,6 +94,35 @@ required: > > - interrupts-extended > > - riscv,ndev > > > > +if: > > + properties: > > + compatible: > > + contains: > > + const: renesas-r9a07g043-plic > > renesas,r9a07g043-plic > ditto. Cheers, Prabhakar
