Hi Rahul, Thank you for the patch! Yet something to improve: [auto build test ERROR on robh/for-next] [also build test ERROR on linus/master v5.19-rc3 next-20220621] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Rahul-T-R/Add-support-for-DPHY-TX-on-J721E/20220622-020528 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next config: hexagon-randconfig-r041-20220622 (https://download.01.org/0day-ci/archive/20220622/202206220747.oBZNVia0-lkp@xxxxxxxxx/config) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project af6d2a0b6825e71965f3e2701a63c239fa0ad70f) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/846aa076b0d86dd2ebc49c2a437c7b452305691d git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Rahul-T-R/Add-support-for-DPHY-TX-on-J721E/20220622-020528 git checkout 846aa076b0d86dd2ebc49c2a437c7b452305691d # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=hexagon SHELL=/bin/bash drivers/phy/cadence/ If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): >> drivers/phy/cadence/cdns-dphy.c:324:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | ^ 1 error generated. vim +/FIELD_PREP +324 drivers/phy/cadence/cdns-dphy.c 285 286 static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 287 { 288 struct cdns_dphy *dphy = phy_get_drvdata(phy); 289 struct cdns_dphy_cfg cfg = { 0 }; 290 int ret, band_ctrl; 291 unsigned int reg; 292 293 ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); 294 if (ret) 295 return ret; 296 297 /* 298 * Configure the internal PSM clk divider so that the DPHY has a 299 * 1MHz clk (or something close). 300 */ 301 ret = cdns_dphy_setup_psm(dphy); 302 if (ret) 303 return ret; 304 305 /* 306 * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes 307 * and 8 data lanes, each clk lane can be attache different set of 308 * data lanes. The 2 groups are named 'left' and 'right', so here we 309 * just say that we want the 'left' clk lane to drive the 'left' data 310 * lanes. 311 */ 312 cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT); 313 314 /* 315 * Configure the DPHY PLL that will be used to generate the TX byte 316 * clk. 317 */ 318 cdns_dphy_set_pll_cfg(dphy, &cfg); 319 320 band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); 321 if (band_ctrl < 0) 322 return band_ctrl; 323 > 324 reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | 325 FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); 326 writel(reg, dphy->regs + DPHY_BAND_CFG); 327 328 return 0; 329 } 330 -- 0-DAY CI Kernel Test Service https://01.org/lkp
