On Tue, 21 Jun 2022 at 22:30, Robert Marko <robimarko@xxxxxxxxx> wrote: > > IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. > Gen2 one is already supported, so add the support for the Gen3 one. > It uses the same register layout as IPQ6018. > > Signed-off-by: Robert Marko <robimarko@xxxxxxxxx> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > --- > Changes in v3: > * Remove parsing QMP pipe clock rate from DT, and instead use the rate > as set in the PHY config > > Changes in v2: > * Rebase onto next-20220621 to apply on the refactored driver > * Remove non existant has_phy_com_ctrl and has_lane_rst -- With best wishes Dmitry
