Hello Shawn, just a ping on this.
Francesco
On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote:
> Update SPI CAN controller clock to match current hardware design.
>
> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 0d84d29e70f1..d309bc0ab8f6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -32,10 +32,10 @@ backlight: backlight {
> };
>
> /* Fixed clock dedicated to SPI CAN controller */
> - clk20m: oscillator {
> + clk40m: oscillator {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> - clock-frequency = <20000000>;
> + clock-frequency = <40000000>;
> };
>
> gpio-keys {
> @@ -194,7 +194,7 @@ &ecspi3 {
>
> can1: can@0 {
> compatible = "microchip,mcp251xfd";
> - clocks = <&clk20m>;
> + clocks = <&clk40m>;
> interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_can1_int>;
> --
> 2.34.1
>
