Hi Rob,
Please neglect this, i picked up old patch.
Will resend this series, with correct device tree patch.
Regards,
Bharat
>
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functionality at Gen5 speed.
>
> Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
>
> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>
> ---
> .../bindings/pci/xilinx-versal-cpm.yaml | 48 +++++++++++++++++--
> 1 file changed, 44 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index cca395317a4c..80597f2974e5 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -14,17 +14,27 @@ allOf:
>
> properties:
> compatible:
> - const: xlnx,versal-cpm-host-1.00
> + contains:
> + enum:
> + - xlnx,versal-cpm-host-1.00
> + - xlnx,versal-cpm5-host
>
> reg:
> items:
> - description: CPM system level control and status registers.
> - description: Configuration space region and bridge registers.
> + - description: CPM5 control and status registers.
> + minItems: 2
>
> reg-names:
> - items:
> - - const: cpm_slcr
> - - const: cfg
> + oneOf:
> + - items:
> + - const: cpm_slcr
> + - const: cfg
> + - items:
> + - const: cpm_slcr
> + - const: cfg
> + - const: cpm_csr
>
> interrupts:
> maxItems: 1
> @@ -95,4 +105,34 @@ examples:
> interrupt-controller;
> };
> };
> +
> + cpm5_pcie: pcie@fcdd0000 {
> + compatible = "xlnx,versal-cpm5-host";
> + device_type = "pci";
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + interrupts = <0 72 4>;
> + interrupt-parent = <&gic>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
> + <0 0 0 2 &pcie_intc_1 1>,
> + <0 0 0 3 &pcie_intc_1 2>,
> + <0 0 0 4 &pcie_intc_1 3>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0
> 0x10000000>,
> + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0
> 0x80000000>;
> + msi-map = <0x0 &its_gic 0x0 0x10000>;
> + reg = <0x00 0xfcdd0000 0x00 0x1000>,
> + <0x06 0x00000000 0x00 0x1000000>,
> + <0x00 0xfce20000 0x00 0x1000000>;
> + reg-names = "cpm_slcr", "cfg", "cpm_csr";
> +
> + pcie_intc_1: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + };
> + };
> +
> };
> --
> 2.17.1
