Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver

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On Wed, 2022-06-15 at 13:53 +0800, CK Hu wrote:
> Hi, Bo-Chen:
> 
> On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote:
> > From: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> > 
> > This patch adds a embedded displayport driver for the MediaTek
> > mt8195
> > SoC.
> > 
> > It supports the MT8195, the embedded DisplayPort units. It offers
> > DisplayPort 1.4 with up to 4 lanes.
> > 
> > The driver creates a child device for the phy. The child device
> > will
> > never exist without the parent being active. As they are sharing a
> > register range, the parent passes a regmap pointer to the child so
> > that
> > both can work with the same register range. The phy driver sets
> > device
> > data that is read by the parent to get the phy device that can be
> > used
> > to control the phy properties.
> > 
> > This driver is based on an initial version by
> > Jitao shi <jitao.shi@xxxxxxxxxxxx>
> > 
> > Signed-off-by: Markus Schneider-Pargmann <msp@xxxxxxxxxxxx>
> > Signed-off-by: Guillaume Ranquet <granquet@xxxxxxxxxxxx>
> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers]
> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@xxxxxxxxxxxx>
> > ---
> 
> [snip]
> 
> > +
> > +static int mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int
> > pattern)
> > +{
> > +	if (pattern < 0 || pattern > 4) {
> 
> The caller would pass pattern from 0 to 4, so this checking is
> redundant. Remove it and this function would always return true, so
> let
> this function be void.
> 
> Regards,
> CK
> 

Hello CK,

ok, I will do this.

BRs,
Bo-Chen
> > +		drm_err(mtk_dp->drm_dev,
> > +			"Implementation error, no such pattern %d\n",
> > pattern);
> > +		return -EINVAL;
> > +	}
> > +
> > +	/* TPS1 */
> > +	if (pattern == 1)
> > +		mtk_dp_set_idle_pattern(mtk_dp, false);
> > +
> > +	mtk_dp_update_bits(mtk_dp,
> > +			   MTK_DP_TRANS_P0_3400,
> > +			   pattern ?
> > +			   BIT(pattern - 1) <<
> > PATTERN1_EN_DP_TRANS_P0_SHIFT :
> > +			   0,
> > +			   PATTERN1_EN_DP_TRANS_P0_MASK |
> > +			   PATTERN2_EN_DP_TRANS_P0_MASK |
> > +			   PATTERN3_EN_DP_TRANS_P0_MASK |
> > +			   PATTERN4_EN_DP_TRANS_P0_MASK);
> > +	return 0;
> > +}
> 
> 




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