Quoting Rex-BC Chen (2022-05-23 02:33:32) > There are two versions for clock reset register control for MediaTek > SoCs. The old hardware is one bit per reset control, and does not > have separate registers for bit set, clear and read-back operations. > This matches the scheme supported by the simple reset driver. > > However, because we need to use different data structure from > reset_simple_data, we can not use the operation of simple reset > driver. > For this reason, we keep the original functions and name this version > as "MTK_RST_SIMPLE". > > In this patch: > - Add a version enumeration to separate different reset hardware. > - Merge the reset register function of simple and set_clr into one > function "mtk_register_reset_controller". > - Rename input variable "num_regs" to "rst_bank_nr" to avoid > confusion. This variable is used to define the quantity of reset bank. > - Document mtk_reset_version and mtk_register_reset_controller. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@xxxxxxxxxxxx> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> > Tested-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> > --- Applied to clk-next
