On 06/06/2022 19:16, Krzysztof Kozlowski wrote: > On 03/06/2022 04:31, Wangseok Lee wrote: >> Add description to support Axis, ARTPEC-8 SoC. >> ARTPEC-8 is the SoC platform of Axis Communications >> and PCIe phy is designed based on SAMSUNG PHY. > > This does not look like wrapped in Linux commit style. > https://protect2.fireeye.com/v1/url?k=c73ae309-a6470b4e-c73b6846-74fe485fff30-d00b7249c2c0a970&q=1&e=b8b33895-af3d-42ce-80ac-4835057078e7&u=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.18-rc4%2Fsource%2FDocumentation%2Fprocess%2Fsubmitting-patches.rst%23L586 > Ok, i will fix it. >> >> changes since v1 : >> -'make dt_binding_check' result improvement >> -Add the missing property list >> -Align the indentation of continued lines/entries >> >> Signed-off-by: Wangseok Lee <wangseok.lee@xxxxxxxxxxx> >> --- >> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 70 ++++++++++++++++++++++ >> 1 file changed, 70 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml >> new file mode 100644 >> index 0000000..ab9766f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml >> @@ -0,0 +1,70 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: https://protect2.fireeye.com/v1/url?k=8784225c-e6f9ca1b-8785a913-74fe485fff30-b4af51b9b3670f43&q=1&e=b8b33895-af3d-42ce-80ac-4835057078e7&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fphy%2Faxis%2Cartpec8-pcie-phy.yaml%23 >> +$schema: https://protect2.fireeye.com/v1/url?k=f78efaf3-96f312b4-f78f71bc-74fe485fff30-583950d45c073877&q=1&e=b8b33895-af3d-42ce-80ac-4835057078e7&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23 >> + >> +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings > > Same comment as patch #1. > I will remove 'Device Tree Bindings'. >> + >> +maintainers: >> + - Jesper Nilsson <jesper.nilsson@xxxxxxxx> >> + >> +properties: >> + compatible: >> + const: axis,artpec8-pcie-phy >> + >> + reg: >> + items: >> + - description: PHY registers. >> + - description: PHY coding sublayer registers. >> + >> + reg-names: >> + items: >> + - const: phy >> + - const: pcs >> + >> + "#phy-cells": >> + const: 0 >> + >> + clocks: >> + items: >> + - description: PCIe PHY reference clock >> + >> + clock-names: >> + items: >> + - const: ref_clk > > Same comment as patch #1. > Ok, remove _clk. >> + >> + num-lanes: >> + const: 2 >> + >> +required: >> + - compatible >> + - reg >> + - reg-names >> + - "#phy-cells" >> + - clocks >> + - clock-names >> + - num-lanes >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/interrupt-controller/irq.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + artpec8 { > > Same comment as patch #1. > > Ok, modity to 'soc'. >> + #address-cells = <2>; >> + #size-cells = <2>; >> + pcie_phy: pcie-phy@16c80000 { >> + compatible = "axis,artpec8-pcie-phy"; >> + reg = <0x0 0x16c80000 0x0 0x2000>, >> + <0x0 0x16c90000 0x0 0x1000>; >> + reg-names = "phy", "pcs"; >> + #phy-cells = <0>; >> + clocks = <&clock_cmu_fsys 53>; >> + clock-names = "ref_clk"; >> + num-lanes = <2>; >> + }; >> + }; >> +... > > > Best regards, > Krzysztof Thank you for kindness reivew. Best regards, Wangseok Lee
