> From: <Conor.Dooley@xxxxxxxxxxxxx>
> Date: Mon, 6 Jun 2022 16:45:44 +0000
>
> On 06/06/2022 17:29, Mark Kettenis wrote:
> > [PATCH] riscv: dts: startfive: currect number of external interrupts
>
> Just as a nit: s/startfive/starfive
I keep making that typo...
> > The PLIC integrated on the Vic_U7_Core integrated on the StarFive
> > JH7100 SoC actually supports 133 external interrupts. 127 of these
> > are exposed to the outside world; the remainder are used by other
> > devices that are part of the core-complex such as the L2 cache
> > controller. But all 133 interrupts are external interrupts as far
> > as the PLIC is concerned. Fixing the property that specifies the
> > number of external interrupts allows the driver to manage these
> > additional interrupts, whch is important since the interrupts for
> > the L2 cache controller are enabled by default.
>
> This sentence is a little hard to follow, maybe:
> Fix the property so that the driver can manage these additional
> external interrupts, which is important...
Thanks, yes, that is better.
> Also, I suppose:
> Fixes: ec85362fb121 ("RISC-V: Add initial StarFive JH7100 device tree")
Sure.
I'll send out a V2 with a fixed commit message in a week or so.
> > ---
> > arch/riscv/boot/dts/starfive/jh7100.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> > index 69f22f9aad9d..f48e232a72a7 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> > @@ -118,7 +118,7 @@ plic: interrupt-controller@c000000 {
> > interrupt-controller;
> > #address-cells = <0>;
> > #interrupt-cells = <1>;
> > - riscv,ndev = <127>;
> > + riscv,ndev = <133>;
> > };
> >
> > clkgen: clock-controller@11800000 {
> > --
> > 2.36.0
> >
> >
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>
