On Fri, Jun 03, 2022 at 05:48:01PM +0530, Kavyasree Kotagiri wrote:
> LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in
> flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins
> can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on
> functions being configured.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@xxxxxxxxxxxxx>
> ---
> .../bindings/mfd/atmel,flexcom.yaml | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> index 221bd840b49e..6050482ad8ef 100644
> --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml
> @@ -16,7 +16,9 @@ description:
>
> properties:
> compatible:
> - const: atmel,sama5d2-flexcom
> + enum:
> + - atmel,sama5d2-flexcom
> + - microchip,lan966x-flexcom
>
> reg:
> maxItems: 1
> @@ -46,6 +48,21 @@ properties:
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [1, 2, 3]
>
> + microchip,flx-shrd-pins:
> + description: Specify the Flexcom shared pins to be used for flexcom
> + chip-selects.
> + $ref: /schemas/types.yaml#/definitions/uint32
The driver seems to think this is an array.
> + minimum: 0
> + maximum: 20
> +
> + microchip,flx-cs-names:
> + description: Chip select names. "cts", "rts" for flexcom USART "CTS" and
> + "RTS" lines. "cs0", "cs1" for flexcom SPI chip-select lines.
> + items:
> + enum: [ cs0, cs1, cts, rts ]
> + minItems: 1
> + maxItems: 2
> +
> patternProperties:
> "^serial@[0-9a-f]+$":
> description: See atmel-usart.txt for details of USART bindings.
> @@ -80,6 +97,8 @@ examples:
> #size-cells = <1>;
> ranges = <0x0 0xf8034000 0x800>;
> atmel,flexcom-mode = <2>;
> + microchip,flx-shrd-pins = <9>;
> + microchip,flx-cs-names = "cs0";
>
> spi0: spi@400 {
> compatible = "atmel,at91rm9200-spi";
> --
> 2.17.1
>
>
