Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe controller is designed based on Design-Ware PCIe controller. changes since v1 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries Signed-off-by: Wangseok Lee <wangseok.lee@xxxxxxxxxxx> --- .../bindings/pci/axis,artpec8-pcie-ep.yaml | 108 ++++++++++++++++++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 123 +++++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml new file mode 100644 index 0000000..3512e38 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe Controller Device Tree Bindings + +maintainers: + - Jesper Nilsson <jesper.nilsson@xxxxxxxx> + +description: |+ + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: axis,artpec8-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI2) registers. + - description: PCIe address space region. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: addr_space + + interrupts: + maxItems: 1 + + interrupts-names: + items: + - const: intr + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe_clk + - const: dbi_clk + - const: mstr_clk + - const: slv_clk + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie_phy + + num-lanes: + const: 2 + +required: + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - num-lanes + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + artpec8 { + #address-cells = <2>; + #size-cells = <2>; + pcie_ep: pcie-ep@17200000 { + compatible = "axis,artpec8-pcie-ep"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x17201000 0x0 0x1000>, + <0x2 0x00000000 0x6 0x00000000>; + reg-names = "dbi", "dbi2", "addr_space"; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + clocks = <&clock_cmu_fsys 39>, + <&clock_cmu_fsys 38>, + <&clock_cmu_fsys 37>, + <&clock_cmu_fsys 36>; + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk"; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + num-ib-windows = <16>; + num-ob-windows = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml new file mode 100644 index 0000000..945a061 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Artpec-8 SoC PCIe Controller Device Tree Bindings + +maintainers: + - Jesper Nilsson <jesper.nilsson@xxxxxxxx> + +description: |+ + This PCIe host controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: axis,artpec8-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + device_type: + items: + - const: pci + + ranges: + maxItems: 2 + + num-lanes: + const: 2 + + interrupts: + maxItems: 1 + + interrupts-names: + items: + - const: intr + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe_clk + - const: dbi_clk + - const: mstr_clk + - const: slv_clk + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie_phy + +required: + - reg + - reg-names + - device_type + - ranges + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + artpec8 { + #address-cells = <2>; + #size-cells = <2>; + pcie: pcie@17200000 { + compatible = "axis,artpec8-pcie"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x16ca0000 0x0 0x2000>, + <0x7 0x0001e000 0x0 0x2000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = </* non-prefetchable memory */ + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000 + /* downstream I/O */ + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + #interrupt-cells = <1>; + clocks = <&cmu_fsys 39>, + <&cmu_fsys 38>, + <&cmu_fsys 37>, + <&cmu_fsys 36>; + clock-names = "pipe_clk", "dbi_clk", "mstr_clk", "slv_clk"; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + }; + }; +... -- 2.9.5
