On 6/2/22 2:18 PM, Yong Wu wrote:
On Mon, 2022-05-30 at 20:03 +0200, Fabien Parent wrote:
Add IOMMU binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>
---
.../bindings/iommu/mediatek,iommu.yaml | 2 +
include/dt-bindings/memory/mt8365-larb-port.h | 96
+++++++++++++++++++
2 files changed, 98 insertions(+)
create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h
[snip...]
+#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
Remove these. they are no used, right?
AIOT and customers are using the modules and their related IOMMU modules.
DISP0, VENC, VDEC, ISP (CAMSYS), and APU (as far as I know, which should
be VP6?) were all supported.
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0)
+#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(0, 1)
[...]
+/* larb4 */
+#define M4U_PORT_APU_READ MTK_M4U_ID(0, 0)
+#define M4U_PORT_APU_WRITE MTK_M4U_ID(0, 1)
Please remove these two APU definitions. currently these are not
supported.
Kidd, please help to check if APU use these definitions with Yong.
However, I think these are all available to the customers.
Thanks
Macpaul Lin
