Hi Siddharth,
On 31/05/2022 14:12, Siddharth Vadapalli wrote:
> TI's J7200 SoC supports additional PHY modes like QSGMII and SGMII
> that are not supported on earlier SoCs. Add a compatible for it.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> ---
> .../mfd/ti,j721e-system-controller.yaml | 5 ++++
> .../bindings/phy/ti,phy-gmii-sel.yaml | 24 ++++++++++++++++++-
> 2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> index fa86691ebf16..e381ba62a513 100644
> --- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> +++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
> @@ -48,6 +48,11 @@ patternProperties:
> description:
> This is the SERDES lane control mux.
>
> + "phy@[0-9a-f]+$":
> + type: object
> + description:
> + This is the register to set phy mode through phy-gmii-sel driver.
> +
Is this really required? The system controller has 100s of different such registers and it is not practical to mention about all.
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> index ff8a6d9eb153..7427758451e7 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
> @@ -53,12 +53,21 @@ properties:
> - ti,am43xx-phy-gmii-sel
> - ti,dm814-phy-gmii-sel
> - ti,am654-phy-gmii-sel
> + - ti,j7200-cpsw5g-phy-gmii-sel
Why not just "ti,j7200-phy-gmii-sel" so it is consistent naming.
>
> reg:
> maxItems: 1
>
> '#phy-cells': true
>
> + ti,enet-ctrl-qsgmii:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Required only for QSGMII mode. Bitmask to select the port for
> + QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
> + ports automatically. Any of the 4 CPSW5G ports can act as the
> + main port with the rest of them being the QSGMII_SUB ports.
> +
This is weird way of doing things.
The Ethernet controller driver already knows which mode the port is
supposed to operate.
e.g.
+&cpsw0_port1 {
+ phy-handle = <&cpsw5g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+ phy-handle = <&cpsw5g_phy1>;
+ phy-mode = "qsgmii-sub";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>;
And it can convey the mode to the PHY driver via phy_ops->set_mode.
So you should be depending on that instead of adding this new property.
> allOf:
> - if:
> properties:
> @@ -73,6 +82,19 @@ allOf:
> '#phy-cells':
> const: 1
> description: CPSW port number (starting from 1)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - ti,j7200-cpsw5g-phy-gmii-sel
> + then:
> + properties:
> + '#phy-cells':
> + const: 1
> + description: CPSW port number (starting from 1)
> + ti,enet-ctrl-qsgmii:
> + enum: [1, 2, 4, 8]
> - if:
> properties:
> compatible:
> @@ -97,7 +119,7 @@ additionalProperties: false
>
> examples:
> - |
> - phy_gmii_sel: phy-gmii-sel@650 {
> + phy_gmii_sel: phy@650 {
> compatible = "ti,am3352-phy-gmii-sel";
> reg = <0x650 0x4>;
> #phy-cells = <2>;
cheers,
-roger
